1. Field of the Invention
The present invention relates to a circuit for generating a column decoder enable signal in a semiconductor device such as a dynamic random access memory (DRAM), and more particularly, to such a circuit capable of transmitting data on bit lines toward data bus lines at an optimum point time.
2. Description of the Prior Art
For leading data stored in a cell array of a DRAM, generally, one of word the lines in a selected cell array block is first enabled by an input row address signal. Data stored in cells enabled by the word line are then sensed and amplified by bit line sensing amplifiers, respectively, one of the sensed and amplified bit line data is then transmitted to a data bus line of a next stage by a column address signal. In order to transmit the bit line data to the data bus line after the bit line data are sufficiently sensed and amplified in the bit line sensing amplifiers in the above process, it is required to provide a column decoder enable signal enabled at an optimum point in time.
For obtaining a period for sensing and amplifying the bit line data by the sensing amplifiers, conventional methods for enabling column decoders use a circuit modeled by resistance elements, capacitance elements and inverter chains. By such a circuit, the point in time when the column decoder enable signal is enabled is determined. In this case, the modeled circuit involves a time delay that varies depending on the fabrication process, the supply voltage, and the temperature used. Due to such variations in delay time, it is difficult to enable the column decoder enable signal at an optimum point in time in the conventional column decoder enable signal generating circuit. Now, the process of reading data stored in a cell array block by the conventional column decoder enable signal generating circuit will be described, in conjunction with FIG. 1 and FIGS. 2A to 2F.
FIG. 1 is a circuit diagram of a semiconductor memory device, illustrating the process of reading data stored in a cell array block by the conventional column decoder enable signal generating circuit. FIGS. 2A to 2F are timing diagrams of signals generated from various parts of the circuit shown in FIG. 1, respectively.
A spare row enable bar signal generating circuit 12, shown in FIG. 1, receives a row address strobe bar signal /RAS, shown in FIG. 2A, via a row address strobe buffer 11. The spare row enable bar signal generating circuit 12 also receives a row address decoding signal via a decoding signal input stage (not shown). The spare row enable bar signal generating circuit 12 performs a logic combination of the received signals and generates a spare row enable bar signal /SRE having a low logic value as shown in FIG. 2B.
The spare row enable bar signal /SRE is delayed for a predetermined time in a sensing generating enable bar signal generating circuit 13, which includes a word line simulator 14, in order to obtain a timing margin. The sensing generating enable bar signal generating circuit 13 generates a low-logic sensing generating enable bar signal /SG having the form of the spare row enable signal /SRE delayed for the predetermined time, as shown in FIG. 2C. As the sensing generating enable bar signal /SG is inverted into the low logic state, a bit line sensing amplifier array 18, which has been pre-charged with a voltage (Vcc/2) corresponding to half of the supply voltage Vcc by a sensing enable signal /S and a restore enable signal RTO as shown in FIG. 2D, receives the ground voltage GND and the supply voltage Vcc respectively by the sensing enable signal /S and the restore enable signal RTO. As a result, the bit line sensing amplifier array 18 is activated. At the activated state, the bit line sensing amplifier array 18 senses and amplifies true and complementary data on true and complementary bit lines BL and /BL. After a sufficient time to sense and amplify the true and complementary data on the true and complementary bit lines BL and /BL elapses, MOS transistors M11 and M12 are turned on so as to transmit the sensed and amplified true and complementary data to true and complementary data lines DB and /DB, respectively.
For optimizing the turn-on time of the MOS transistors M11 and M12, a chip selector bar signal generating circuit 15 is used which is constituted by inverters and capacitors. An inverter chain is also used. The chip selector enable bar signal generating circuit 15 delays the output signal /SG of the spare row enable bar signal generating circuit 13 for a predetermined time and thereby generates a chip selector bar signal /CS shown in FIG. 2E. The inverter chain inverts and delays the chip selector enable bar signal /CS output from the chip selector bar signal generating circuit 15, thereby generating a global column enable signal YGo having a high logic value, as shown in FIG. 2F. The global column enable signal YGo from the inverter chain is applied to a column decoder array 19. In response to the global column enable signal YGo, the column decoder array 19 transmits a column address decoding signal AYi to gates of the MOS transistors M11 and M12 for a period of time during which the high-logic global column enable signal YGo is applied.
However, a semiconductor device including the conventional column decoder enable signal generating circuit involves the following problems.
First, the data access time is increased because the delay time is estimated depending on simulation of the sensing generating enable bar signal /SG and the chip selector bar signal /CS for a timing of the sensing time for transmitting the bit line data to the data bus line.
Second, the delay time is continuously varied depending on the fabrication process, the supply voltage and the temperature used because the semiconductor device employs inverters and capacitance elements so as to delay the sensing generating enable bar signal /CS and the chip selector enable bar signal /SG for a predetermined time.
Third, where an appropriate delay time is to be obtained, the circuit should be corrected using a mask because the signal delay is accomplished using inverters and capacitors.